1. Field
The present disclosure pertains to the field of memory compression. More particularly, the present disclosure pertains to memory compression utilizing an internal cache residing in main memory.
2. Description of Related Art
Memory compression is utilized for reducing large memory requirements, such as, an enterprise server application by compressing data before storing it into memory. Consequently, a reduction in memory costs, power requirements, and server size is achieved.
Some applications using compressed memory data require different amounts of uncompressed data amounts of cache to alleviate latency impacts. However, typical compression architectures are not flexible for accommodating different cache memory sizes required for different applications.
Typically, memory compression may be achieved by utilizing a separate external Dynamic Random Access Memory (DRAM) for storing frequently accessed uncompressed data for alleviating the impact of decompression latency. For example, the DRAM may be placed outside the memory interface through a separate memory address/data path in order to have a large cache. However, this incurs the extra cost for both the pins for connecting to the external cache and the cost of the external DRAM. Furthermore, an increase in design and validation costs arises because of the need to test and validate the external cache and the additional interface and an increase in material costs due to an increase in board size and power requirements.
Another typical solution is embedded DRAM (eDRAM). However, the current eDRAM solutions (4 and 8 MB) are insufficient to handle server applications that utilize at least 32 MB of memory. In addition eDRAM cache increases the cost of the platform.